Study of Tree Multiplier Using Reversible Logic Gate

---------------------------------------------------------------------***--------------------------------------------------------------------Abstract— The objective of this project is to design high performance arithmetic circuits which are faster and have low power consumption using a new adiabatic logic family of CMOS and to analyze its performance for sequential circuits and effects upon cascading. Reversible logic is widely used in low power VLSI. This adiabatic logic family is best suited to arithmetic circuits because the critical path is made of a long chain of cascaded reversing gates. The more advantage of this logic which is higher speed and low power consumption is observed upon cascading which is more precise, it’s better suitable for arithmetic circuits. The proposed multiplier is better and provides better result in terms of the number of gates, constant inputs, garbage outputs, hardware complexity, and number of transistors required as comparison with the existing circuit. The data relating to the primitive reversible gates which are available in literature and helps researches in designing higher complex computing circuits using reversible gates are represented by this paper.